Yuchen Mei (He/Him)

Education

Stanford University, CA, US - Ph.D. in Electrical Engineering (Sept. 2023 – Present)

Stanford University, CA, US - M.S. in Electrical Engineering (Sept. 2021 – Jun. 2023) - GPA: 4.023/4.3

Nanjing University, China - B.S. in Electronic Information Science and Technology (Sept. 2017 – Jun. 2021) - GPA: 4.62/5

The University of British Columbia (UBC), Canada - Exchange Student (Jul. 2019 – Aug. 2019)

Research Experience

Stanford University - Research Assistant

Aug. 2022 – Dec. 2022 | Advisor: Priyanka Raina

• Optimized the place-and-route tool for CGRA applications, doubling frequency of image processing applications.
• Advanced systolic array placements for ResNet-18, boosting frequency from ~200MHz to ~500MHz.

Apple, Sunnyvale - CAD Engineer Intern

Jun. 2024 – Sep. 2024

• Built machine learning framework to predict ECO transformations, achieving <2% error across multiple partitions.

Publications

• “Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications,” IEEE VLSI Symposium, 2024.
• “Cascade: An Application Pipelining Toolkit for CGRAs,” IEEE TCAD, 2024.

Professional Skills

• Languages & Environments: Verilog/SystemVerilog, Python, C/C++, MATLAB, LINUX, Docker
• Design Tools: Synopsys Design Compiler, Cadence Innovus, Xilinx Vivado, Intel Quartus, ModelSim

Honors & Awards

• Special Prize for Excellent Undergraduate Thesis, Nanjing University, 2021
• Baosteel Outstanding Student Scholarship, China, 2020
• Outstanding Winner, Interdisciplinary Contest in Modeling, USA, 2019